Learn the basics of FPGA configuration and programming. This section focuses on the features available in FPGAs.
You will gain a deep understanding of the configuration flow, examine the status and control registers for monitoring configuration status, and review best practices for configuration debugging.

Gain an in-depth understanding of design constraints and timing constraints methodology. Understand design constraint input options, design constraint precedence rules and their impact on design implementation, and learn about the Constraints Propagation Engine (CPE). Get recommendations and tips on what to watch out for when defining design and timing constraints.

We will introduce you to all the features and tools available in Lattice's Propel design environment. You will learn about the various features available in the Propel Builder and the Propel SDK (Software Development Kit) while explaining the development flow. Examples include flexible IP integration using the IP Catalog, managing system memory during firmware development, using OpenOCD (on-chip debugging) for debugging, and TCL scripting of the development flow.

This course introduces the external memory interfaces supported by CertusPro-NX FPGAs. The course begins with an overview of DDR/LPDDR features and specifications. It then describes how to implement DDR/LPDDR memory interfaces in a design using all architectural blocks, the memory controller subsystem, and with proper initialization and training.

This course introduces various techniques for developing designs to be implemented in FPGAs. The course will explain basic concepts and considerations to keep in mind and provide ideas for optimizing your design for speed, area, power, or reliability. clock domain crossing (CDC) is an important consideration when implementing your design in FPGAs, and you will learn about CDC Learn about solutions that can be used to overcome CDC issues. Best practices for designing more stable and optimized FPGA implementations will be presented.

Learn how Lattice's Propel simplifies the development of FPGA-based processor systems and SoC designs (System-on-Chip). This course provides a high-level introduction to Propel and demonstrates its capabilities.

Introducing Lattice Radiant design software. We will introduce an easy-to-use design environment that includes powerful design and intelligent planning tools, advanced optimization engines and analysis tools, and real-time debugging capabilities for more accurate designs.

Interested in implementing PCIe using Lattice FPGAs? This course will cover the basics of the PCIe protocol, including understanding the PCIe protocol stack, how to perform packet construction, link training and enumeration, and interrupt and error handling. how to configure Lattice IP to build PCIe solutions Learn how you can configure Lattice IP to build PCIe solutions and get debugging tips to solve common problems.